This invention relates to semiconductor devices, and more particularly to improved step coverage for metal contacts and interconnections for semiconductor integrated circuits.
In the past ten years, semiconductor memory devices have increased in density from 4K bit devices designed in 1972 to 256K and 1 megabit devices being designed in 1982, employing semiconductor chips of about the same size. To accomplish this, line resolution has been reduced to about 2 micron or less. In manufacture of these VLSI semiconductor devices, a thin metal coating such as aluminum is deposited and patterned to create contacts and interconnections. Problems occur in thinning of the narrow metal strip at near-vertical steps or sidewalls. Thinner metal at these steps or sidewalls results in higher resistance and a propensity for electro-migration failures. Heretofore, the steepness of the sidewalls has been minimized by a "reflow" process, but this necessitates phosphorous-doped silicon oxide and undesirable high temperature operations, as well as larger geometries.
It is the principal object of this invention to provide an improved process for making VLSI type semiconductor integrated circuits; particularly for improving step coverage. Another object is to provide improved semiconductor devices with conductor or metallization patterns which avoid thinning at steps and discontinuities. A further object is to provide improved step coverage and lower resistance for metallization of semiconductor devices.